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AT86RF231
A security operation can be started within one SRAM access by appending the start command
AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register
AES_CTRL_MIRROR is a mirrored version of register 0x83 (AES_CTRL).
Figure 11-1. ECB Programming SPI Sequence - Encryption
byte 0 (cmd.)
byte 1 (address)
byte 2 (AES cmd)
byte 3 (data)
byte 18 (data)
byte 19 (AES cmd)
0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
data_0[7:0]
data_15[7:0]
1 0 0 0 0 0 0 0
SRAM write
0x83
ECB, encryption
AES start
Summarizing, the following steps are required to perform a security operation using only one
SPI access:
1. Configure SPI Access
2. Configure AES Operation
3. Write 128-bit data block
4. Start AES Operation
a) SRAM Write, refer to Section 6.2.3
b) Start Address 0x83
Address 0x83: select ECB mode, direction
Addresses 0x84 - 0x93: either plain or ciphertext
Addresses 0x94: start AES operation, ECB mode
This sequence is recommended because the security operation is configured and started within
one SPI transaction.
The ECB encryption operation is illustrated in Figure 11-2 on page 130 . Figure 11-3 on page 130
shows the ECB decryption mode, which is supported in a similar way.
Figure 11-2. ECB Mode - Encryption
Plaintext
Plaintext
Encryption
Key
Block Cipher
Encryption
Ciphertext
Encryption
Key
Block Cipher
Encryption
Ciphertext
Figure 11-3. ECB Mode - Decryption
Ciphertext
Ciphertext
Decryption
Key
Block Cipher
Decryption
Plaintext
Decryption
Key
Block Cipher
Decryption
Plaintext
130
8111C–MCU Wireless–09/09
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